Nxp-semiconductors P89LPC9321 UM10310 Manual de usuario Pagina 79
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UM10310 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 1 November 2010 79 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
Table 73. Master Transmitter mode
Status code
(I2STAT)
Status of the I
2
C
hardware
Application software response Next action taken by I
2
C
hardware
to/from I2DAT to I2CON
STA STO SI AA
08H A START
condition has
been transmitted
Load SLA+W x 0 0 x SLA+W will be transmitted;
ACK bit will be received
10H A repeat START
condition has
been transmitted
Load SLA+W or
Load SLA+R
x 0 0 x As above; SLA+W will be
transmitted; I
2
C-bus switches
to Master Receiver Mode
18h SLA+W has been
transmitted; ACK
has been received
Load data byte or000xData byte will be transmitted;
ACK bit will be received
no I2DAT action
or
100xRepeated START will be
transmitted;
no I2DAT action
or
010xSTOP condition will be
transmitted;
STO flag will be reset
no I2DAT action 110xSTOP condition followed by a
START condition will be
transmitted; STO flag will be
reset.
20h SLA+W has been
transmitted;
NOT-ACK has
been received
Load data byte or000xData byte will be transmitted;
ACK bit will be received
no I2DAT action
or
100xRepeated START will be
transmitted;
no I2DAT action
or
010xSTOP condition will be
transmitted; STO flag will be
reset
no I2DAT action 110xSTOP condition followed by a
START condition will be
transmitted; STO flag will be
reset
28h Data byte in
I2DAT has been
transmitted; ACK
has been received
Load data byte or000xData byte will be transmitted;
ACK bit will be received
no I2DAT action
or
100xRepeated START will be
transmitted;
no I2DAT action
or
010xSTOP condition will be
transmitted; STO flag will be
reset
no I2DAT action 110xSTOP condition followed by a
START condition will be
transmitted; STO flag will be
reset
- P89LPC9321 User manual 1
- Contact information 2
- 1. Introduction 3
- 1.2 Pin description 5
- 1.3 Functional diagram 8
- 1.4 Block diagram 9
- NXP Semiconductors 10
- 1.6 Memory organization 20
- 2. Clocks 21
- 2.4 Clock output 22
- 3. Interrupts 25
- 4. I/O ports 28
- 4.1 Port configurations 29
- 4.4 Input-only configuration 31
- 4.7 Additional port features 32
- 5.1 Brownout detection 33
- 5.2 Power-on detection 34
- 5.3 Power reduction modes 34
- 6. Reset 37
- 6.1 Reset vector 38
- 7. Timers 0 and 1 39
- 7.1 Mode 0 40
- 7.2 Mode 1 40
- 002aae091 44
- 8.2 Changing RTCS1/RTCS0 45
- 9.3 Basic timer operation 48
- 9.4 Output compare 50
- 9.5 Input capture 52
- 9.6 PWM operation 52
- 002aaa893 53
- 002aaa894 53
- 9.7 Alternating output mode 54
- 9.9 HALT 55
- 9.10 PLL operation 55
- 10. UART 59
- 10.4 Mode 3 60
- 10.5 SFR space 60
- 10.8 Framing error 61
- 10.9 Break detect 61
- 10.10 More about UART Mode 0 63
- 002aaa925 64
- 002aaa926 65
- 002aaa927 65
- 10.14 Break detect 66
- 10.15 Double buffering 66
- C interface 70
- C data register 71
- C slave address register 71
- C control register 72
- C Status register 73
- C operation modes 74
- 002aaa900 85
- 12.1 Configuring the SPI 88
- 12.4 Mode change on SS 89
- 12.5 Write collision 90
- 12.6 Data mode 90
- 13. Analog comparators 94
- 13.3 Comparator input pins 96
- 13.4 Comparator interrupt 96
- 14. Keypad interrupt (KBI) 100
- 15. Watchdog timer (WDT) 101
- 002aae092 102
- 5 PRE+() 103
- 15.3 Watchdog clock source 105
- 16. Additional features 107
- 16.2 Dual Data Pointers 108
- 16.1 Software reset 108
- 17. Data EEPROM 109
- 17.1 Data EEPROM read 110
- 17.2 Data EEPROM write 110
- 17.3 Hardware reset 111
- 17.6 Data EEPROM Row Fill 111
- 18. Flash memory 112
- 18.7 Boot ROM 117
- 18.13 IAP authorization key 122
- 18.14 Flash write enable 122
- 18.16 IAP error status 123
- 18.18 User security bytes 128
- 18.19 Boot Vector register 129
- 18.20 Boot status register 129
- 19. Instruction set 131
- 20. Legal information 134
- 21. Tables 135
- 22. Figures 137
- 23. Contents 138
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